A three-dimensional memory device including vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Memory stack structures may be formed on a semiconductor chip through an alternating stack of insulating layers and electrically conductive layers that function as word lines. Various additional structures vertically extend through the alternating stack. Local variations in the material composition in the memory stack structures may induce stress that deforms or warps the semiconductor wafer upon which structures are formed. The deformation or warping may cause difficulty in subsequent processing steps that may include chip bonding or packaging.